# Simulation

To simulate the written module, you have to write a function that will test the module by reading the output signals and will draw numbers as segments in a system terminal.
Create directory lab3 and create file lab3.py in created directory. Copy and paste a source code from below to the file lab3.py.

```
#!/usr/bin/env python3

from migen import *

from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster

# IOs ----------------------------------------------------------------------------------------------

_io = [
    # Clk / Rst
    ("clk10", 0, Pins("N5"),  IOStandard("3.3-V LVTTL")),
    ("clk50", 0, Pins("P11"), IOStandard("3.3-V LVTTL")),
    ("clk50", 1, Pins("N14"), IOStandard("3.3-V LVTTL")),

    # Seven Segment
    ("seven_seg", 0, Pins("C14 E15 C15 C16 E16 D17 C17 D15"), IOStandard("3.3-V LVTTL")),
    ("seven_seg", 1, Pins("C18 D18 E18 B16 A17 A18 B17 A16"), IOStandard("3.3-V LVTTL"))
]

# Platform -----------------------------------------------------------------------------------------

class Platform(AlteraPlatform):
    default_clk_name   = "clk50"
    default_clk_period = 1e9/50e6
    create_rbf         = False

    def __init__(self, toolchain="quartus"):
        AlteraPlatform.__init__(self, "10M50DAF484C7G", _io, toolchain=toolchain)
        self.add_platform_command("set_global_assignment -name FAMILY \"MAX 10\"")
        self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF")
        self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"")

    def create_programmer(self):
        return USBBlaster()

    def do_finalize(self, fragment):
        AlteraPlatform.do_finalize(self, fragment)
        self.add_period_constraint(self.lookup_request("clk10",    loose=True), 1e9/10e6)
        self.add_period_constraint(self.lookup_request("clk50", 0, loose=True), 1e9/50e6)
        self.add_period_constraint(self.lookup_request("clk50", 1, loose=True), 1e9/50e6)

# Design -------------------------------------------------------------------------------------------
class HexDisp(Module):
      def __init__(self, output_hex0, output_hex1):
        hex0 = Signal(8)
        hex1 = Signal(8)

        self.output_hex0 = output_hex0
        self.output_hex1 = output_hex1

        self.comb += hex0[0].eq(1)
        self.comb += hex0[1].eq(0)
        self.comb += hex0[2].eq(0)
        self.comb += hex0[3].eq(1)
        self.comb += hex0[4].eq(1)
        self.comb += hex0[5].eq(0)
        self.comb += hex0[6].eq(0)
        self.comb += hex0[7].eq(1)

        self.comb += hex1[0].eq(0)
        self.comb += hex1[1].eq(0)
        self.comb += hex1[2].eq(1)
        self.comb += hex1[3].eq(0)
        self.comb += hex1[4].eq(0)
        self.comb += hex1[5].eq(1)
        self.comb += hex1[6].eq(0)
        self.comb += hex1[7].eq(1)

        self.comb += self.output_hex0.eq(hex0)
        self.comb += self.output_hex1.eq(hex1)

def disp(hex, line):
       print("")

def HexDisp_test(dut):
    hex_0 = yield hex0
    hex_1 = yield hex1
    for x in range(5):
       disp(hex_1,x)
       disp(hex_0,x)
       print("")

# Build --------------------------------------------------------------------------------------------
if __name__ == "__main__":
# Create our platform (fpga interface)
    platform = Platform()
    hex0 = platform.request("seven_seg",0)
    hex1 = platform.request("seven_seg",1)

# Create our module (fpga description)
    module=HexDisp(hex0, hex1)
    run_simulation(module, HexDisp_test(module))
```
When you run this source code you should see an empty line in the terminal.

## Tasks

Write by yourself a code to **disp(hex, line)** function. This funtion draws a part of letter defined as **hex**, drawen part is choosen by **line**.
Make changes and run lab3.py you should achieve a result similar to below.

```
 _    
  || |
 _  _ 
|    |
 _    
```

Overrite existing code in lab3.py by copy and paste module written by you in lab2.py, copy only module and IOs. Next rebuild HexDisp_test(dut) to draw date. A result for a date 05.05.24 you can see below.
```
 _  _  _  _  _    
| ||  | ||    || |
    _     _  _  _ 
| |  || |  ||    |
 _  _. _  _. _    

```