# System on a chip

## Adding IPCore to SoC

Edit ~/litex/litex-boards/litex_boards/targets/terasic_de10lite.py, add new package and modify a BaseSoC class.

```
from litex.soc.cores.hexdisp import HexDisp
```

```
class BaseSoC(SoCCore):
    def __init__(self, sys_clk_freq=50e6,
        with_led_chaser     = True,
        with_disp           = True,
        with_video_terminal = False,
        **kwargs):
        platform = terasic_de10lite.Platform()

        # CRG --------------------------------------------------------------------------------------
        self.crg = _CRG(platform, sys_clk_freq)

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on DE10-Lite", **kwargs)

        # SDR SDRAM --------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
            self.add_sdram("sdram",
                phy           = self.sdrphy,
                module        = IS42S16320(sys_clk_freq, "1:1"),
                l2_cache_size = kwargs.get("l2_size", 8192)
            )

        # Video Terminal ---------------------------------------------------------------------------
        if with_video_terminal:
            self.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
            self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")

        # Leds -------------------------------------------------------------------------------------
        if with_led_chaser:
            self.leds = LedChaser(
                pads         = platform.request_all("user_led"),
                sys_clk_freq = sys_clk_freq)

        if with_disp:
            self.disp = HexDisp(
                output_hex0 = platform.request("seven_seg",0),
                output_hex1 = platform.request("seven_seg",1),
                output_hex2 = platform.request("seven_seg",2),
                output_hex3 = platform.request("seven_seg",3),
                output_hex4 = platform.request("seven_seg",4),
                output_hex5 = platform.request("seven_seg",5))
```

## Compiling a software
Create a directory lab5 and copy files from ~/litex/litex/litex/soc/software/demo into it. Then compile the software and program the board with the new software.

```
python3 -m litex_boards.targets.terasic_de10lite --build
export SOC_DIRECTORY=~/litex/litex/litex/soc
python3 demo.py --build-path=build/terasic_de10lite/ --mem=rom
python3 -m litex_boards.targets.terasic_de10lite --integrated-rom-init=demo.bin --build --load
```

## Tasks

In file build/terasic_de10lite/software/include/generated/csr.h in lab5 directory you can find functions to control disp_hex.
Define a new function in disp.c file, that will set the current date on 7-seg displays, if you will have a problem you can check implementation of **static void led_cmd(void)** in main.c. On the basis of disp.c add new command to main.c that will print the date in terminal. To compile disp.c with rest of files you have to modify the Makefile.